The present invention relates to chemical mechanical polishing pads and methods of forming the polishing pads. More particularly, the present invention relates to poromeric chemical mechanical polishing pads and methods of forming poromeric polishing pads.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited onto and removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting and dielectric materials may be deposited using a number of deposition techniques. Common deposition techniques in modern wafer processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) and electrochemical plating, among others. Common removal techniques include wet and dry isotropic and anisotropic etching, among others.
As layers of materials are sequentially deposited and removed, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., photolithography) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful for removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize or polish work pieces such as semiconductor wafers. In conventional CMP, a wafer carrier, or polishing head, is mounted on a carrier assembly. The polishing head holds the wafer and positions the wafer in contact with a polishing layer of a polishing pad that is mounted on a table or platen within a CMP apparatus. The carrier assembly provides a controllable pressure between the wafer and polishing pad. Simultaneously, a polishing medium (e.g., slurry) is dispensed onto the polishing pad and is drawn into the gap between the wafer and polishing layer. To effect polishing, the polishing pad and wafer typically rotate relative to one another. As the polishing pad rotates beneath the wafer, the wafer sweeps out a typically annular polishing track, or polishing region, wherein the wafer's surface directly confronts the polishing layer. The wafer surface is polished and made planar by chemical and mechanical action of the polishing layer and polishing medium on the surface.
The CMP process usually occurs on a single polishing tool in two or three steps. The first step planarizes the wafer and removes the bulk of the excess material. After the planarization, the subsequent step or steps remove scratches or chattermarks introduced during the planarization step. The polishing pads used for these applications must be soft and conformal to polish the substrate without scratching. Furthermore, these polishing pads and slurries for these steps often require selective removal of material, such as a high TEOS to metal removal rate. For purposes of this specification, TEOS is the decomposition product of tetraethyloxysilicate. Since TEOS is a harder material than metals such as copper, this is a difficult problem that manufacturers have been addressing for years.
Over the last several years, semiconductor manufacturers have been moving increasingly to poromeric polishing pads, such as Politex™ and Optivision™ polyurethane pads for finishing or final polishing operations in which low defectivity is a more important requirement (Politex and Optivision are trademarks of Dow Electronic Materials or its affiliates.). For purposes of this specification the term poromeric refers to porous polyurethane polishing pads produced by coagulation from aqueous solutions, non-aqueous solutions or a combination of aqueous and non-aqueous solutions. The advantage of these polishing pads is that they provide efficient removal with low defectivity. This decrease in defectivity can result in a dramatic wafer yield increase.
A polishing application of particular importance is copper-barrier polishing in which low defectivity is required in combination with the ability to remove both copper and TEOS dielectric simultaneously, such that the TEOS removal rate is higher than the copper removal rate to satisfy advanced wafer integration designs. Commercial pads such as Politex polishing pads do not deliver sufficiently low defectivity for future designs nor is the TEOS:Cu selectivity ratio high enough. Other commercial pads contain surfactants that leach during polishing to produce excessive amounts of foam that disrupts polishing. Furthermore, the surfactants may contain alkali metals that can poison the dielectric and reduce the semiconductor's functional performance.
Despite the low TEOS removal rate associated with poromeric polishing pads, some advanced polishing applications are moving toward all-poromeric pad CMP polishing operations because of the potential of achieving lower defectivity with poromeric pads versus other pad types such as IC1000™ polishing pads. Although these operations provide low defects, the challenges remain to further decrease pad-induced defects and to increase polishing rate.